1. Field of the Invention
The present invention relates to the field of semiconductor processing, and more particularly to a method for increasing transistor density in an integrated circuit through the use of partial layering of the transistors.
2. Description of the Related Art
Integrated circuits are widely employed in a variety of electronics applications to produce complex electronic circuits on an extremely small area of a monolithic semiconductor substrate, such as silicon. Universally recognized for their low cost, high speed, low power dissipation, and high reliability, semiconductor integrated circuits long ago replaced discrete components as the predominant and preferred electronic devices. World-wide sales of integrated circuits have increased exponentially since the early 1960s. During this time, semiconductor manufacturers have strived to reduce the cost and increase the complexity of integrated circuits by fabricating a larger number of transistors in a given area of the semiconductor substrate. The primary means of achieving these goals has been reducing the size of the individual transistors that comprise the integrated circuit. Smaller transistors enable the fabrication of more complex and smaller devices. Smaller devices have the dual benefits of increasing the number of devices manufacturable on a single semiconductor wafer and increasing the probability that any individual device on a given silicon wafer will be free of random fatal defects. Since the early 1960s, when the average feature size or design rule within the industry was approximately 25 microns, the average design rule has decreased rather steadily by approximately 11% per year. The average design rule dropped below one micron in the mid 1980s, and has been decreasing steadily since then.
In addition to the size of the transistors themselves, the amount of area required to isolate individual transistors from one another limits the transistor density, i.e. the number of transistors per unit area. Referring to FIG. 1, a conventional integrated circuit is shown in which a first transistor 10 and a second transistor 12 are fabricated on a semiconductor substrate 8. To isolate first transistor 10 from second transistor 12, an isolation structure such as shallow trench isolation structure 14 is required to prevent the inadvertent coupling of source/drain region 16 of first transistor 10 and source/drain region 18 of second transistor 12. The lateral dimension d.sub.L of isolation structure such as shallow trench isolation structure 14 limits the density of transistors that can be fabricated over a given area of substrate 8. As a rule of thumb, the minimum lateral dimension d.sub.L necessary to adequately ensure proper isolation between source/drain region 16 of first transistor 10 and source/drain region 18 of second transistor 12 is approximately equal to the lateral dimension L.sub.t of first transistor 10. Shallow trench isolation structure 14 occupies a region of substrate 8 that could otherwise be devoted to the formation of active transistors and represents a limitation on the achievable transistor density. It would, therefore, be highly desirable to implement a circuit design and fabrication technique to reduce or eliminate the percentage of substrate 8 occupied by isolation regions 14.